1. Field of the Invention
The present invention relates to a memory circuit, and particularly to a memory circuit that can be capable of being quickly written in/read data.
2. Description of the Prior Art
When an application unit coupled to a memory circuit needs to write data to memory cells corresponding to a word line WL1 of a segment of a bank of the memory circuit, a controller of the memory circuit first enables an active command ACTWL1 (as shown in FIG. 1) corresponding to an address of the word line WL1. Then, after the controller enables the active command ACTWL1, a word line switch corresponding to the word line WL1 can be turned on according to the active command ACTWL1. After the controller enables the active command ACTWL1, the controller enables a write command WRC. After the controller enables the write command WRC, bit switches of memory cells of the segment MS1 corresponding to the word line WL1 can be turned on according to the write command WRC, wherein a number of the bit switches of the memory cells of the segment MS1 corresponding to the word line WL1 is M, and M is an integer greater than 1. Therefore, after the bit switches of the memory cells of the segment MS1 are turned on, the data can be written into the memory cells of the segment MS1 corresponding to the word line WL1 in turn.
As shown in FIG. 1, because the bit switches are turned on according to the write command WRC, the write command WRC needs to include M clock signals making the bit switches be turned on after the active command ACTWL1, wherein time for writing the data into the memory cells corresponding to the word line WL1 at least includes time of the M clock signals and time of the active command ACTWL1. In addition, after the write command WRC, the controller can enable a pre-charge command PREC corresponding to an address of the word line WL1, and the word line switch corresponding to the word line WL1 is turned off according to the pre-charge command PREC.
As shown in FIG. 1, if the application unit needs to write the data to memory cells corresponding to a word line WLM of the segment, the above mentioned steps for writing the data to the memory cells corresponding to the word line WL1 need to be executed again. That is to say, although the application unit writes the same data (the data) to the memory cells corresponding to the word line WLM, writing the same data (the data) to the memory cells corresponding to the word line WLM still needs to at least take the time of the M clock signals and the time of the active command ACTWL1, wherein FIG. 1 illustrates a timing of the active commands ACTWL1, ACTWLM, the write command WRC, and the pre-charge command PREC enabled by the controller of the memory circuit. Therefore, the prior art is not a good operation method for the memory circuit.